The present invention relates to a semiconductor device, in particular to a layout structure of a bottom gate type MIS (Metal Insulator Semiconductor) formed in a wiring layer.
A technology of forming an active element having switch function and rectification function in a wiring layer is known like a semiconductor device described in Japanese Unexamined Patent Publication No. 2010-141230 (refer to Patent Literature 1). By forming an active element in a wiring layer, it is possible to change the function of a whole semiconductor device significantly without changing the layout of a semiconductor element formed over a semiconductor substrate.
FIG. 1 is a view showing an example of the structure of a semiconductor device described in Patent Literature 1. In FIG. 1, a semiconductor device described in Patent Literature 1 has a wiring layer 900 and a semiconductor element 910 formed over a semiconductor substrate. The wiring layer 900 has an insulation film 921 formed over a diffusion prevention film 901 and a wire 904 and a via 903 embedded in the insulation film 921. A barrier metal not shown in the figure is formed at an interface between the wire 904 and the via 903 and other structures (the insulation film 921, the diffusion prevention film 901, and the wire 904). A diffusion prevention film 911 is formed over the wiring layer 900 and an insulation film 922 and a wire 916 and a via 915 embedded in the insulation film 922 are formed over the diffusion prevention film 911. The semiconductor element 910 has a gate electrode 902, a gate insulation film 911, and a semiconductor layer 912. The semiconductor layer 912 is formed over the gate insulation film 911 and coupled to a wire 914 through a via 913. The gate electrode 902 is formed under the gate insulation film 911 in the wiring layer 900. A barrier metal not shown in the figure is formed at an interface between the wire 914 and the via 913 and other structures (the insulation film 922 and the semiconductor layer 912).